Semiconductor memory

ABSTRACT

A plurality of memory cell arrays each having a plurality of memory cells and a plurality of word lines the word lines are driven by drive circuits which share the driving operation, and permit reading out from and writing into the memory cells connected to the word lines WL to be driven. These drive circuits are respectively connected to main word lines WLO, which are driven by decoding the entered address information in a decoding circuit whereby the drive circuits are driven. Since the main word lines WLO are formed with a third metal wiring layer, a wiring of the word lines can be formed with a gate wiring layer of a transistor and a first metal wiring layer and wiring of a line control circuit can be formed with a second metal wiring layer which intersects the word lines thereby reducing delay operation of the memory.

FIELD OF THE INVENTION

The present invention relates to a semiconductor memory such as adynamic random access memory (hereafter referred to as a "DRAM").

BACKGROUND ART

The following reference describes a conventional DRAM:

Reference: 1992 Symposium on VLSI Circuits Digest of Technical PapersIEEE "A Boosted Dual Word-Line Decoding Scheme for 256 Mb DRAMs" P.112-113 (K. Noda et al.)

The memory cell area of the conventional DRAM described in thisreference is divided by a plurality of memory arrays. This DRAM isprovided with a plurality of bit line couples and a plurality of wordlines which are intersection-arranged on respective memory cell arrays.Each memory cell array is provided with word line drive circuits fordriving the word lines. These word line drive circuits are providedalong a plurality of memory arrays. In addition, this DRAM has senseamplifiers connected to a plurality of bit line couples. These senseamplifiers are provided in parallel with the word lines. Line decodersare provided along the word line drive circuits near this memory cellarea. These line decoders are used to select the main word lines. Aplurality of drive signal generating circuits are arranged concentratedat one-side ends of the word line drive circuits near the memory cellarea. These drive signal generating circuits are for supplying the drivesignals to a plurality of word line drive circuits.

In this DRAM, a main word line is selected by boosting one of the mainword lines to a voltage VBOOT, which is higher than the power supplyvoltage VCC, by the line decoder. Thus the word line drive circuitsconnected to the selected main word line become ready to operate. Adrive signal generating circuit operates in response to a specifiedaddress signal to supply a drive signal to the specified word line drivecircuit. The word line drive circuits to which the drive signal issupplied boost the specified word lines connected thereto to the voltageVBOOT and the data stored in the memory cells connected to these wordlines is outputted to the bit line couples.

Lately, semiconductor memories such as the DRAM have been demanded toprovide higher operating speeds along with the increased storagecapacities.

An object of the present invention is to provide a semiconductor memorywhich has implements high speed operation.

SUMMARY OF THE INVENTION

A semiconductor memory comprising semiconductors as a first aspect ofthe present invention made to fulfill the above-described objectcomprises a plurality of bit lines; a plurality of word lines arrangedintersecting these bit lines; first and second memory cell arrays havinga plurality of memory cells connected to the bit lines and the wordlines and arranged at the intersections of these bit lines and wordlines; a first drive circuit arranged adjacent to the first memory cellarray to drive part of the word lines; a second drive circuit arrangedadjacent to the second memory cell array to drive the other part of theword lines; a third drive circuit for driving those word lines arrangedadjacent to the word lines to be driven by the first and second drivecircuits; a main word line which connects the first, second and thirddrive circuits to each other, a line control circuit for selecting a bitline according to address information to be entered, and a decodingcircuit for decoding the address information and driving the main wordlines, wherein the wiring of the word lines is formed by a gate wiringlayer of transistors and a first metal wiring layer connected to thisgate wiring layer, the wiring of the line control circuit is formed by asecond metal wiring layer which is arranged on the first metal wiringlayer and intersects the word lines, and the wiring of the main wordlines is formed by a third metal wiring layer which is arranged on thesecond metal wiring layer parallel to the word lines of the first memorycell array and the word lines of the second memory cell array.

With the above, the improvement for higher operation speed isimplemented.

To achieve the above-described object, a second aspect of the presentinvention comprises a plurality of bit lines; a plurality of word linesarranged intersecting these bit lines; a memory cell array having aplurality of memory cells connected to the bit lines and the word linesand arranged at the intersections of these bit lines and word lines; aplurality of drive circuits for driving the word lines; a main word linewhich connects the plurality of drive circuits to each other; a decodingcircuit for decoding the address information to be entered and drivingthe main word lines; and a level shift circuit for boosting a specifiedmain word line to a higher voltage than a power supply voltage accordingto an output of the decoding circuit, wherein the plurality of drivecircuits are respectively connected to the boosted voltage and theground voltage, each being formed by an inversion circuit for reversingthe boosted voltage of the main word lines and a word line drive circuitfor driving a specified word line according to the output of theinversion circuit.

With the above, the improvement for higher operation speed isimplemented.

Furthermore, to achieve the above-described object, a third aspect ofthe present invention comprises a plurality of bit lines; a plurality ofword lines arranged to intersect these bit lines; a memory cell arrayhaving a plurality of memory cells connected to the bit lines and theword lines and arranged at the intersections of these bit lines and wordlines; a plurality of drive circuits for driving the word lines; a mainword line which connects the plurality of drive circuits to each other;and a decoding circuit for decoding the address information to beentered and driving the main word lines, wherein the plurality of drivecircuits respectively comprise a level shift circuit for boosting aspecified main word line to a boosted voltage higher than the powersupply voltage according to the output of the decoding circuit and aword line drive circuit for driving a specified word line according tothe output of the level shift circuit and the level shift circuitcomprises a latch circuit comprising first and second transistors whichhave a gate electrode and a drain electrode which are cross-connectedand a source electrode which receives the boosted voltage, a thirdtransistor which is connected in series between the drain electrode ofthe first transistor and the main word lines receives the ground voltageat the gate electrode, and a switching circuit which is connected to thedrain electrode of the second transistor and the ground voltage and isoperated with the voltage of the main word line.

With the above, the improvement for higher operation speed isimplemented.

Furthermore, to achieve the above-described object, a fourth aspect ofthe present invention comprises a plurality of bit lines; a plurality ofword lines arranged intersecting these bit lines; a memory cell arrayhaving a plurality of memory cells connected to the bit lines and theword lines and arranged at the intersections of these bit lines and wordlines; a plurality of drive circuits for driving the word lines; a mainword line which connects the plurality of drive circuits to each other;a first decoding circuit for decoding the address information to beentered and driving the main word lines; and a second decoding circuitfor decoding the address information and supplying a drive signal to thedrive circuits for driving the word lines corresponding to the addressinformation, wherein the plurality of drive circuits respectivelycomprise the first transistor which has a source electrode connected tothe main word line and a gate electrode which receives the groundvoltage, the second transistor which has a source electrode connected tothe second decoding circuit, a drain electrode connected to the wordlines and a gate electrode connected to the drain electrode of the firsttransistor, and a switching circuit which is connected to the word linesto supply the ground voltage to the word lines in response to thevoltage of the main word line.

With the above, the improvement for higher operation speed isimplemented.

Furthermore, to achieve the above-described object, a fifth aspect ofthe present invention comprises a plurality of bit lines; at least firstand second word lines arranged to intersect these bit lines; a memorycell array having a plurality of memory cells connected to the bit linesand the word lines and arranged at the intersections of these bit linesand word lines; a plurality of drive circuits for driving the wordlines; a main word line which connects the plurality of drive circuitsto each other; a first decoding circuit for decoding the addressinformation to be entered and driving the main word lines; and secondand third decoding circuits for decoding the address information andsupplying drive signals to the drive circuits for driving the word linescorresponding to the address information, wherein the plurality of drivecircuits respectively comprise an inversion circuit which receives ahigher boosted voltage than the power supply voltage and the groundvoltage and inverts the voltage of the main word line and the first andsecond word line drive circuits for driving the specified word lines inresponse to the output of the inversion circuit, the first word linedrive circuit is controlled by the output of the second word line drivecircuit, and the second word line drive circuit is controlled by theoutput of the third decoding circuit.

With the above, the improvement for higher operation speed isimplemented.

Furthermore, to achieve the above-described object, a sixth aspect ofthe present invention comprises a plurality of bit lines; a plurality ofword lines arranged intersecting these bit lines; a memory cell arrayhaving a plurality of memory cells connected to the bit lines and theword lines and arranged at the intersections of these bit lines and wordlines; a plurality of drive circuits arranged adjacent to the memorycell array to drive the corresponding word lines, respectively; and aplurality of decoding circuits for supplying drive signals to the drivecircuits for driving the word lines corresponding to the addressinformation, wherein the plurality of decoding circuits are respectivelyarranged at both sides of the plurality of drive circuits.

With the above, the improvement for higher operation speed isimplemented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a configuration block diagram of a main part of asemiconductor memory showing a first embodiment of the presentinvention;

FIGS. 2, 2a and 2b are cross-sectional views taken along the lines 2--2,2a--2a and 2b--2b of FIG. 1;

FIG. 3 is a configuration block diagram of a main part of asemiconductor memory showing a second embodiment of the presentinvention;

FIG. 4 is a circuit diagram of a drive circuit shown in FIG. 3;

FIG. 5 is a circuit diagram of a drive circuit shown in FIG. 1, showinga third embodiment of the present invention;

FIG. 6 is a circuit diagram of a drive circuit shown in FIG. 1, showinga fourth embodiment of the present invention;

FIG. 7 is a circuit diagram of a drive circuit shown in FIG. 1, showinga fifth embodiment of the present invention; and

FIG. 8 is a configuration block diagram of a main part of asemiconductor memory showing a sixth embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention is described in detail referring to theaccompanying drawings. In the description, a DRAM is used as asemiconductor memory.

FIG. 1 is a configuration block diagram of a main part of a DRAM showinga first embodiment of the present invention.

This DRAM is provided with memory cell arrays 100a and 100b for storinga plurality of data (though two memory cell arrays are shown in FIG. 1,the number of the arrays is not limited). Each of the memory cell arrays100a and 100b is divided into a plurality of memory cell blocks and hasa plurality of word lines WL and bit line couples (not shown) arrangedto intersect the plurality of word lines WL. Memory cells 9 are locatedin each of the memory cell blocks and are respectively connected tointersections of the word lines WL and the bit lines. Drive circuitgroups 200a, 200b and 200c (though three drive circuit groups are shownin FIG. 1, the number of groups is not limited to this) for driving theword lines WL are alternately arranged at both sides of the memory cellarrays, respectively. Each of the drive circuit groups 200a, 200b and200c respectively comprise a plurality of drive circuits such as drivecircuits 201a, 102b and 201c. The drive circuits 201a, 201b and 201cdrive some of the word lines driven by the drive circuit groups 200a,200b and 200c and other word lines WL are driven by other drivecircuits, not shown. A plurality of main word lines WLO are connected toa decoder circuit 400 which drives the drive circuits in groups 200a,200b and 200c and a string decoder (not shown. The decoder circuit 400decodes address information to be entered and functions to selectivelydrive a main word line WL0 corresponding to this address informationwhich is selected from the plurality of main word lines WLO. Inaddition, this DRAM has a line control circuit (not shown) for selectingand driving the bit lines.

The operation of the DRAM having the above configuration is describedbelow. An address information which designates a memory cell 9 whichreceives a read or write request is entered and a specified main wordline WLO is selected and driven in response to this address information.The drive circuits 201a, 201b and 201c of the drive circuit groups 200a,200b and 200c which are connected to the main word lines WLO when thesemain word lines WLO are driven selectively actuate a plurality of wordlines WL. The memory cells connected to the driven word lines WL areactivated to be ready for read and write operations. Read and writeoperations are carried out by sending the data stored in the memorycells to the bit line couples or write data from the bit line couples tothe memory cells.

In this case, the wiring configuration of the DRAM shown in FIG. 1 isdescribed referring to FIG. 2. FIG. 2 is a cross sectional view takenalong the line 2--2 of in FIG. 1.

Wiring layers or gate electrode lines 102 for the gate electrodes of aplurality of MOS transistors 11 forming the memory cells a are formed ona semiconductor substrate 101. The bit lines BL are formed substantiallyorthogonal to the wiring layers 102, and a first insulation layer 103 isinterposed between the wiring layers 102 and the bit lines BL. A secondinsulation layer 105 and storage electrodes 104 are formed on bit linesBL. In addition, a plurality of word lines WL, which comprise metallayers, are formed on the second insulation layer 105 to intersectsubstantially orthogonally the bit lines (which are substantiallyparallel to the metal wiring layer 102 for the gate electrodes). On thesecond insulation layer 105 and the word lines WL, a line control line107, which is an element of a line control circuit made of metal layers,is formed to substantially orthogonally intersect the plurality of wordlines WL (which are substantially parallel to the bit lines BL) througha third insulation layer 106. On this line control line 107, a pluralityof main word lines WLO made of metal layers is formed through a fourthinsulation layer 108. In this case, the plurality of word lines WL andwiring layers 102 for the gate electrodes are kept in contact with eachother by using an area shown in FIG. 2a between memory cell blocks inthe memory cell arrays (i.e., areas where the memory cell arrays are notformed, so that the sectional view thereof shows no bit lines BL orstorage electrodes 104; instead the area has a contact part 10 forconnecting the word lines WL and the wiring layers 102 for the gateelectrodes). Also, field oxide regions 12 are formed under the wiringlayers 102. These wiring layers 102 for the gate electrodes are used toas a connection the word lines WL. As described above, the parasiticresistance and parasitic capacity of the word lines WL can be reduced ascan the delay in signal transmission through the word lines WL, byreducing the number of memory cells driven by one word line drivecircuit. This is accomplished by dividing each drive circuit into aplurality of word line drive circuits and connecting these word linedrive circuits to the main word lines WLO, and by forming the word linesWL connected with the wiring layers 102 for the gate electrodes withoutforming the word lines WL only.

FIG. 2b is a cross sectional view similar to FIG. 2a in that it is takenalong a line 2b--2b of FIG. 1 where memory cells are not formed. Thewiring layers in FIG. 2b, both those having contact with word lines WLan those having no contact with word lines WL, have the same crosssectional shapes as those shown in FIG. 2a. The wiring layers 102 inregions where transistors are formed and in regions where contacts withword lines are made are relatively thick, whereas the wiring layers 102in regions where no contacts with word lines are made are relativelythin, and appear in two parts in the cross sectional views FIGS. 2a and2b.

A second embodiment of the present invention is described below.

FIG. 3 is a configuration block diagram of a main part of a DRAM showinga second embodiment of the present invention. In FIG. 3, the samecomponent parts as in FIG. 1 are given the same reference numerals.

The second embodiment is characterized in that the decoding circuit 400comprises an address decoding circuit 410 for decoding addressinformation to be entered and a level shifting circuit 420 forlevel-shifting the output of the address decoding circuit 410 andsupplying the output thereof to the main word lines WLO, as shown inFIG. 3.

The drive circuits 201a, 201b and 201c comprising drive circuit groups200a, 200b and 200c each have the same circuit configuration as shown inFIG. 4. In FIG. 4, each of the drive circuits comprises an inversion orbuffer circuit 210 which inverts the output voltage of the main wordline WL0 and supplies the inverted output voltage to a node N210 and aplurality of word line drive circuits 220a and 220b (though two circuitsare shown in FIG. 4, the number of circuits is not limited to this)which operate in response to the voltage at the node N210.

The inversion circuit 210 comprises a P-type MOS transistor (hereafterreferred to as "PMOS") 211 and an N-type MOS transistor (hereafterreferred to as "NMOS") 212. A boosted voltage VBOOT which is boostedhigher than the power supply voltage VCC is supplied to the sourceelectrode of PMOS 211, and the drain electrode of PMOS 211 is connectedto the node N210. The gate electrode thereof is connected to the mainword line WL0. A ground voltage VSS is supplied to the source electrodeof NMOS 212 and the drain electrode of NMOS 212 is connected to the nodeN210. The gate electrode thereof is connected to the main word line WL0.Therefore, the inversion circuit 210 supplies the ground voltage VSS tothe node 210 when the main word lines WLO remain at a high voltage level(a voltage level at which NMOS 212 can be sufficiently activated;hereafter referred to as "H" level) and a boosted voltage VBOOT to thenode N210 when the main word line WL0 remains at a low voltage level (avoltage level at which PMOS can be sufficiently activated; hereafterreferred to as "L" level).

The word line drive circuit 220a comprises a MOS transistor, PMOS 221a,NMOS 222a and NMOS 223a. The source electrode of PMOS 221a is connectedto the drive signal line PW1 and the drain electrode thereof isconnected to the word line WL1. The gate electrode thereof is connectedto the node N210. The ground voltage VSS is supplied to ,the sourceelectrode of NMOS 222a and the drain electrode thereof is connected tothe word line WL1. The gate electrode thereof is connected to the nodeN210. The ground voltage VSS is supplied to the source electrode of NMOS223a and the drain electrode thereof is connected to the word line WL1.The gate electrode thereof is connected to an inversion drive signalline PW1/having a complementary voltage value with respect to the nodedrive signal line PW1.

The word line drive circuit 220b has a circuit configuration similar tothe word line drive circuit 220a in which the MOS transistors PMOS 221b,NMOS 222b and NMOS 223b correspond respectively to PMOS 221a, NMOS 222aand NMOS 223a, and the word line WL1, the drive signal line PW1 and theinversion drive signal line PW1/in the word line drive circuit 220acorrespond respectively to the word line WL2, the drive signal line PW2and the inversion drive signal line PW2/. The word line drive circuits220a and 220b respectively supply the voltages of the drive signal linesPW1 and PW2 to the word lines WL1 and WL2 when the ground voltage VSS issupplied to the node N210, and supply the ground voltage VSS to the wordlines WL1 and WL2, when the boosted voltage VBOOT is supplied to thenode N210.

An example of the operating conditions for the drive circuit is, thefollowing drive signal PW1=VBOOT, inversion drive signal PW1/=VSS, drivesignals PW2˜PWn=VSS, and inversion drive signals PW2/˜PWn/=VCC. Underthese conditions, when the main word lines WLO have the "H" level, theword line drive circuits 220a and 220b operate and voltages VBOOT andVSS are respectively supplied to the word lines WL1 and WL2.Accordingly, the memory cells connected to the word line WL1 areactivated to permit reading from and writing into these memory cells.

In the second embodiment, the level shifting circuit is incorporated inthe decoding circuit 400 and is not provided in the drive circuits 201a,201b and 201c. Accordingly, the component devices of the circuit can bereduced in number and the output voltage level need not be shifted ineach drive circuit and therefor the word lines WL can be startedquickly.

In these embodiment, no circuit terminal has a higher voltage than theboosted voltage VBOOT during operation from selection of the main wordline WL0 by the decoding circuit 400 to starting of the word lines bythe drive circuits 201a, 201b and 201c. Consequently, a high withstandvoltage gate oxide film need not be used in MOS transistors which formthe drive circuits.

In addition, the drive circuits 201a, 201b and 201c are not providedwith a normally-on type NMOS to the gate electrode of which the boostedvoltage VBOOT is always supplied and the main word line WLO is connectedto the ground voltage. Therefore, the voltage boosting capacity of thewhole DRAM is small and power consumption can be reduced.

Furthermore, since one main word line WLO is connected to each four wordlines WL in the drive circuit groups 200a, 200b and 200c, the wiringpitch (interval) of the main word lines WL0 on the memory cell arrays100a and 100b can be large and the width of the wiring of the main wordlines WL0 can also be large to have a low resistance.

A third embodiment according to the present invention is describedbelow.

FIG. 5 is a circuit diagram of the drive circuit which shows the thirdembodiment according to the present invention.

This drive circuit conforms to the drive circuits 201a, 201b and 201cshown in FIG. 1. This drive circuit comprises a level shifting circuit230 for shifting the voltage level of the main word lines WL0 andoutputting this level-shifted voltage to the node N230 and the word linedrive circuits 220a and 220b (though two word line drive circuits areshown in FIG. 5, the number of circuits is not limited to this) whichare connected to the node N230 and drive the word lines WL1 and WL2,respectively, in response to the voltage at the node N230. Since thecircuit configuration of these word line drive circuits 220a and 220b isthe same as that shown in FIG. 4, the same reference numerals are usedand the description is omitted.

The level shifting circuit 230 is composed of two PMOS 231 and PMOS 232transistors, a transfer gate 233 composed of a depression type NMOStransistor, and a switching circuit 234. The boosted voltage VBOOT issupplied to the source electrodes of PMOS 231 and 232 which form a latchcircuit. The drain electrode of PMOS 231 is connected to the gateelectrode of PMOS 232 and the gate electrode of PMOS 231 is connected tothe drain electrode of PMOS 232 and the node N230. The source electrodeof the NMOS which forms the transfer gate 233 is connected to the mainword line WL0 and the drain electrode thereof is connected to the drainelectrode of PMOS 231. The ground voltage VSS is supplied to the gateelectrode of NMOS 233. This transfer gate 233 cinducts current even whenthe voltage VGS across the gate and source electrodes is 0V and isinactive when the voltage VGS across the gate and source electrodes is aspecified voltage lower than 0V. The switching circuit 234 operates withthe voltage of the main word line WL0 and the boosted voltage VBOOT issupplied to the node N230. Accordingly, the word line drive circuits220a and 220b do not drive the word lines when the main word line is notselected.

When the main word line WL0 is selected and starts from the groundvoltage VSS, the switching circuit 234 is activated and the voltage ofthe node N231 begins to rise. At this time, the transfer gate 233 is cutoff when the voltage of the main word line WL0 becomes the specifiedvoltage between the ground voltage VSS and the power supply voltage VCC.In addition, when the voltage of the main word line WL0 becomes close tothe power supply voltage VCC, the boosted voltage VBOOT appears on thenode N231 and PMOS 232 becomes inactive. Therefore, the voltage of thenode N230 becomes the ground voltage VSS and the word line drivecircuits 220a and 220b drive the word lines. In addition, PMOS 231becomes activated with the voltage of the node N230 to supply theboosted voltage VBOOT to the node N231 to maintain the voltage of thenode N231.

As described above, since the main word lines WL0 need not have theboosted voltage VBOOT, these drive circuits can quickly set the groundvoltage VSS at the node N230. The voltage of the node N230 begins torise when the switching circuit 234 is activated and simultaneously thecurrent of PMOS 232 is reduced and therefore a wasteful passing-throughcurrent is not produced and the operation can be speeded up.

Moreover, the level shifting circuit 230 to which the boosted voltageVBOOT is supplied is not provided with the normally-on type NMOS to thegate electrode of which the boosted voltage VBOOT is supplied andtherefore power consumption can be reduced.

In addition, a higher voltage than the boosted voltage VBOOT is notsupplied to the drive circuits and therefore the high withstand voltageoxide film need not be used in MOS transistors which form the drivecircuit.

Moreover, the level shifting circuit 230 is formed with four MOStransistors and the area it occupies is small.

Furthermore, since one main word line WL0 is connected to each four wordlines WL in the drive circuit groups 200a, 200b and 200c, the wiringpitch (interval) of the main word lines WL0 on the memory cell arrays100a and 100b can be large and the wiring width of the main word linesWL0 can be wide to have a low resistance.

The level shifting circuit 230 in these drive circuits can apply to thedrive signal generating-circuit which supplies the drive signal PW forselecting the word line drive circuits 220a and 220b.

A fourth embodiment according to the present invention is describedbelow.

FIG. 6 is a circuit diagram showing the fourth embodiment according tothe present invention.

This drive circuit 201 corresponds to the drive circuit 201a, 201b or201c shown in FIG. 1. The drive circuit 201 is connected with drivesignal lines PW1, PW2 and PW3 for transmitting drive signals to beoutputted from a plurality of drive signal generating circuits 500a,500b and 500c (though three circuits are shown in FIG. 6, the number ofcircuits is not limited to this) which decode the address informationand generate the drive signals for driving the word lines WL.

The drive circuit 201 comprises an inverter 240, two transfer gates 241and 251 composed of depression type NMOS transistors, two NMOStransistors 242 and 252 and two switching circuits 243 and 253. Theinverter 240 inverts the voltage of the main word lines WL0 and suppliesthe inverted voltage to the node N240. The source electrodes of the NMOStransistors which form the transfer gates 241 and 251 are respectivelyconnected to the main word lines WL0, the drain electrodes thereof arerespectively connected to the nodes N241 and N251, and the groundvoltage VSS is supplied to the gate electrodes thereof. The sourceelectrodes of NMOS 242 and NMOS 252 are respectively connected to thedrive signal lines PW1 and PW2, the drain electrodes thereof arerespectively connected to the word lines WL1 and WL2 and the gateelectrodes thereof are respectively connected to the nodes N241 andN251. The NMOS transistors which form the transfer gates 241 and 251conduct current even when the voltage VGS across the gate the sourceelectrodes is 0V and maintain the property that the transfer gatesbecome inactive when the voltage VGS across the gate and sourceelectrodes is a specified voltage lower than 0V. The switching circuits243 and 253 respectively operate in response to the voltage of the nodeN240.

Operation of this drive circuit 201 is described below. The main wordlines WL0 have the ground voltage VSS at the initial state. At thistime, the transfer gates 241 and 251 conduct current and therefore thenodes N241 and N251 have the ground voltage VSS. In this case, thevoltage of the node N240 is the power supply voltage VCC. NMOStransistors 242 and 252 become inactive and the switching circuits 243and 253 are activated in response to the voltages of the nodes N240,N241 and N252. Consequently, the word lines WL1 and WL2 have the groundvoltage VSS.

The main word line WL0 is selected and started from the ground voltageVSS and the transfer gates 241 and 251 are cut off when the voltage ofthe main word line WL0 is a specified voltage between the ground voltageVSS and the power supply voltage VCC. In addition, when the voltage ofthe main word line WL0 is the power supply voltage VCC, the voltage ofthe main word line WL0 is inverted by the inverter 240 and the node N240has the ground voltage VSS and therefore the switching circuits 243 and253 become inactive. At this time, if, for example, the word line drivesignal generating circuit 500a is selected and the boosted voltage VBOOTis supplied to the drive signal line PW1, the voltage to the node N240is boosted to a voltage higher than VBOOT+VTN (VTN is a thresholdvoltage of NMOS 242). When the voltage of this node N241 is boosted,NMOS 242 supplies this boosted voltage VBOOT to the word line WL1. Withthis, the memory cell connected to the word lines WL1 is activated topermit reading from and writing into this memory cell.

As described above, this drive circuit 201 is able to start the wordlines WL1 and WL2 without applying the boosted voltage to the main wordlines WL0, and the operation speed is raised.

Since this drive circuit 201 is not provided with the normally-on typeNMOS to the gate electrode to which the boosted voltage VBOOT issupplied, the capacity for boosting the whole DRAM is small andtherefore power consumption can be reduced.

In addition, one main word line WL0 is only connected to each four wordlines WL in the drive circuit 201 and the wiring pitch (interval) of themain word lines WL0 on the memory arrays 100a and 100b can be set to belarge and therefore the wiring width of the main word lines WL0 can bewide to reduce the resistance thereof.

A fifth embodiment according to the present invention is describedbelow.

FIG. 7 is a circuit diagram of a drive circuit 201 showing the fifthembodiment according to the present invention.

This drive circuit corresponds to the drive circuits 201a, 201b and 201cshown in FIG. 1. The drive circuit 201 is provided with two drive signallines for transmitting drive signals to be outputted from a plurality ofdrive signal generating circuits 500a and 500b (though two circuits areshown in FIG. 7, the number of circuits is not limited to this) whichdecode the address information and generate the drive signals fordriving the word lines WL.

The drive circuit 201 comprises an inversion or buffer circuit 210 forinverting the voltage of the main word lines WL0 and supplying thisinverted voltage to the node N210 and a plurality of word line drivecircuits 220c and 220d (though two circuits are shown in FIG. 7, thenumber of circuits is not limited to this) which operate in response tothe voltage of the node N210.

The inversion circuit 210 comprises PMOS 211 and NMOS 212 and has acircuit configuration similar to t he .inversion circuit 210 shown inFIG. 4. Consequently, the inversion circuit 210 supplies the groundvoltage VSS to the node N210 when the voltage of the main word linesremains at "H" level and the boosted voltage VBOOT to the node N210 whenthe voltage of the main word lines remains at "L" level.

The word line drive circuits 220c and 220d have a similar circuitconfiguration, respectively, and the description in this case is made ofthe word line drive circuit 220c. The word line drive circuit 220ccomprises PMOS 221c and two NMOS 222c and 223c. The source electrode ofPMOS 221c is connected to the drive signal line of the drive signalgenerating circuit 500a and the drain electrode thereof is connected tothe word lines WL1. The gate electrode thereof is connected to the nodeN210. The ground voltage VSS is supplied to the source electrodes ofNMOS 222c and 223c and the drain electrodes thereof are respectivelyconnected with the word lines WL1. The gate electrode of NMOS 222c isconnected to the node N210 and the gate electrode of NMOS 223c isconnected to the drive signal line of the drive signal generatingcircuit 500b. The word line drive circuit 220d has a circuitconfiguration similar to that of the word line drive circuit 220c andthree MOS transistors, PMOS 221d, NMOS 222d and NMOS 223d, are providedrespectively corresponding to PMOS 221c, NMOS 222c and NMOS 223c. Theword line WL1 in the word line drive circuit 220c and the drive signalgenerating circuits 500a and 500b correspond to as the word line WL2,and the drive signal generating circuits 500b and 500a. Consequently,the word line drive circuits 220c and 220d respectively supply thevoltages of the signal drive lines of the drive signal generatingcircuit 500a and 500b to the word lines WL1 and WL2 when the groundvoltage VSS is supplied to the node N210 and the ground voltage VSSrespectively to the word lines WL1 and WL2 when the boosted voltageVBOOT is supplied to the node N210.

Operation of this drive circuit 201 is described below. The main wordlines WL0 are given the ground voltage VSS in the initial condition.Therefore, the boosted voltage VBOOT is supplied to the node N210 by theinversion circuit 210 and the word line drive circuit 220c and 220drespectively supply the ground voltage VSS to the word lines WL1 andWL2.

When the main word line WL0 is selected and the voltage of the main wordline WL0 becomes the boosted voltage VBOOT, the ground voltage VSS issupplied to the node N210 by the inversion circuit 210. The PMOS 221cand 221d transistors of the word line drive circuits 220c and 220d areactivated and NMOS 222c and 222d transistors are made inactive inresponse to the voltage of the node N210. When, for example, the drivesignal generating circuit 500a is selected, the boosted voltage VBOOT issupplied to the drive signal line of the drive signal generating circuit500a. In this case, the drive signal generating circuit 500b is notselected and therefore the ground voltage VSS is supplied to the drivesignal line of the drive signal generating circuit 500b. Therefore, NMOS223c of the word line drive circuit 220c is made inactive. The boostedvoltage of the drive signal line of the drive signal generating circuit500a is supplied to the word lines WL1 connected thereto and the memorycell connected to this word line WL1 is activated to permit reading fromand writing into this memory cell. In this case, NMOS 223d of the wordline drive circuit 220d remains activated and the ground voltage-VSS issupplied to the word line WL2 to prevent a faulty operation (multipleselection of the word lines).

As described above, the word line drive circuits 220c and 220d of thisdrive circuit 201 are provided with NMOS 223c and 223d transistors whichsupply the ground voltage VSS to the word lines, which are not selected,in response to the voltage of the drive signal line and therefore the,inversion drive signal line for supplying the inversion drive signal isunnecessary and the chip size in the direction of the word line can bereduced.

In addition, one main word line WL0 is only connected to each four wordlines WL in the drive circuit 201 and the wiring pitch (interval) of themain word lines WL0 on the memory arrays 100a and 100b can be set to belarge and therefore the wiring width of the main word lines WL0 can bewide to reduce the resistance thereof.

A sixth embodiment according to the present invention is describedbelow.

FIG. 8 is a circuit diagram of the main part of the drive circuitshowing the sixth embodiment according to the present invention.

This DRAM is provided with memory cell arrays 100a to 100f (though sixmemory cell arrays are shown in FIG. 8, the number of the memory cellarrays is not limited to this) for storing a plurality of data. Each ofthe memory cell arrays 100a to 100f is divided into a plurality ofmemory cell blocks and has a plurality of word lines WL and bit linecouples (not shown) which are arranged to intersect the plurality ofword lines WL. Memory cells (not shown) are respectively connected tothe intersections of these word lines WL and the bit lines. Drivecircuit groups 200a to 200i (though nine drive circuit groups areprovided in FIG. 8, the number of groups is not limited to this) fordriving respective word lines WL are alternately arranged at both sidesof each of the memory cell arrays. For example, the drive circuit groups200a and 200d are arranged at both sides of the memory cell array 100a.The drive circuit groups 200a to 200f respectively drive the word linesWL and, for example, the drive circuit groups 200a and 200d drive theword lines WL in the memory cell array 100a and the drive circuit groups200d and 200g drive the word lines WL in the memory cell array 100d. Aplurality of main word lines WL0 are connected to the decoding circuit400 which drives the drive circuit groups 200a to 200f and a stringdecoder (not shown). For example, a main word line WL0 is connected tothe drive circuit groups 200a, 200d and 200g. The decoding circuit 400functions to decode address information entered and selectively drivethe main word line WL0 corresponding to this address information fromthe plurality of main word lines WL0. In addition, this DRAM has a linecontrol circuit (not shown) for driving the bit lines. Moreover, thesixth embodiment is characterized in that there are arranged drivesignal generating circuits 500a to 5001, which form sub decodingcircuits, for decoding the address information and driving the drivesignal line PW which supplies the drive signal to the word lines WLcorresponding to the address information at both sides of the drivecircuits 200a to 200i (not adjacent to the memory cell arrays 100a to100f). For example, the drive signal generating circuits 500a and 500brespectively supply the drive signal to the drive circuit 200a whichdrives the word lines WL of the drive circuit 200a. Sense amplifiers300a to 300h for amplifying a difference of voltage values between thebit line couples are arranged at both sides of respective memory cellarrays 100a to 100f.

Operation of this DRAM is described below. For example, the drive signalgenerating circuit 500b supplies selectively the drive signal to thedrive signal lines PW2 and PW3 according to the address information.With this drive signal supplied, the drive circuits 200a and 200b supplythe boosted voltage VBOOT to the word lines WL in the memory cell arrays100a and 100b to permit reading out from and writing into the memorycell array connected to the boosted word lines WL.

In this DRAM, the drive signal generating circuits 500a to 5001 arearranged at both sides of the drive circuits 200a to 200i and thereforedrive signal generating circuits can be provided without increasing thearea of the chip.

Since the parasitic capacity and the parasitic resistance of the wiringof one drive line are reduced, the operating speed can be raised andpower consumption can be reduced.

The present invention which has been described in detail above is notlimited to the above-described embodiments. The present inventionenables various modifications such as, for example, modification orchange of the configuration and arrangement of the whole DRAM intodifferent modes from those in the drawings or application tosemiconductor memories other than the DRAM specified in the presentinvention.

INDUSTRIAL APPLICABILITY

As described in detail above, the embodiments according to the presentinvention enable increases the speed of data read and write operations.

The second and fourth embodiments enable the provision of higherwithstand voltage and lower power consumption.

The third embodiment enables the provision of higher withstand voltage,lower power consumption and greater reduction of chip size.

The fifth and sixth embodiments further enable the provision of lowerpower consumption and greater reduction of chip size.

What is claimed is:
 1. A semiconductor memory for storing data,comprising:a first wiring layer which includes a pair of bit lines fortransferring data, said first wiring layer extending in a firstdirection; a plurality of word lines formed by a second wiring layerextending in a second direction substantially orthogonal to that of saidpair of bit lines; a memory cell array comprising a plurality of memorycells, each of said memory cells being connected to said pair of bitlines and a word line at intersections of said pair of bit lines andsaid word line, each memory cell having a transistor; and a gateelectrode line extending in said second direction parallel to and spacedfrom said word lines, said gate electrode line being connected to a gateelectrode of the transistor of said memory cell, wherein said gateelectrode line is connected to said word lines at a region other than aregion wherein a memory cell is formed by a third wiring layer extendingin a third direction substantially orthogonal to said first and seconddirections.
 2. A semiconductor memory according to claim 1, furthercomprising:a drive circuit group comprising drive circuits for drivingsaid word lines; a decoding signal transferring line connected to saiddrive circuits for the activation thereof; and a decoding circuit fordecoding address information and for outputting a selection signal toselect said decoding signal transferring line.
 3. A semiconductor memoryaccording to claim 2, wherein said plurality of word lines includesfirst and second word lines, and said drive circuit group includes afirst drive circuit driving said first word line and a second drivecircuit driving said second word line, said first and second drivecircuits being connected to said decoding signal transferring line.
 4. Asemiconductor memory for storing data, comprising:a pair of bit linesextending in a first direction for transferring data; a plurality ofword lines extending in a direction substantially orthogonal to that ofsaid pair of bit lines; a memory cell array comprising a plurality ofmemory cells, each of said memory cells being connected with said pairof bit lines and a word line and arranged at intersections of said pairof bit lines and said word line; a drive circuit for driving a wordline, said drive circuit comprisinga first transistor of a firstconductivity type having a first electrode connected to a first drivesignal line having a first voltage level, a second electrode connectedto said word line and a gate electrode connected to an output node of abuffer circuit; a second transistor of a second conductivity type havinga gate electrode connected to the output node of said buffer circuit;and a third transistor of said second conductivity type having a firstelectrode supplied by the ground voltage, a second electrode connectedto said word line and a gate electrode connected to a second drivesignal line having a second voltage level complementary to that of saidfirst drive signal line; a decoding signal transferring line connectedto said drive circuit for the activation thereof; a first decodingcircuit for decoding address information and for outputting a selectionsignal for selecting said decoding signal transferring line; a levelshifting circuit for boosting said decoding signal transferring line toa boosted voltage higher than a power supply voltage in response to saidselection signal, said boosted voltage being supplied to said buffercircuit for outputting an output signal at said output node thereof,said output signal consisting of said boosted voltage or said groundvoltage in response to a voltage on said decoding signal transferringline, said drive circuit driving said word line in response to theoutput signal at the output node of said buffer circuit.
 5. Asemiconductor memory according to claim 4, wherein said level shiftingcircuit comprisesa latch circuit includingfirst and second transistorsof a first conductivity type, each of said first and second transistorshaving a first electrode connected to said boosted voltage, a gateelectrode and a second electrode, said gate and second electrode of saidfirst transistor being connected to the second and gate electrodes ofsaid second transistor respectively, and said second electrode of saidsecond transistor being connected to an input of said drive circuit; athird transistor of said second conductivity type having a firstelectrode connected to the second electrode of said first transistor anda gate electrode supplied with said ground voltage; and a switchingcircuit connected between the second electrode of said second transistorand said ground voltage for operating in response to a voltage on saidmain word line.
 6. A semiconductor memory according to claim 4, whereinsaid plurality of word lines includes first and second word lines, andsaid drive circuit includes a first word line drive circuit for drivingsaid first word line and a second word line drive circuit for drivingsaid second word line, said first and second word line drive circuitsbeing connected to said decoding signal transferring line.
 7. Asemiconductor memory according to claim 6, further comprising:a seconddecoding circuit for decoding said address information and for supplyinga first drive signal to drive said first word line via said drivecircuit in response to said address information; and a third decodingcircuit for decoding said address information and for supplying a seconddrive signal to drive said second word line via said drive circuit inresponse to said address information; and wherein said drive circuitincludesa first transistor having a first electrode connected to saiddecoding signal transferring line and a gate electrode receiving aground voltage; a second transistor having a first electrode forreceiving said first drive signal, a second electrode connected to saidfirst word line and a gate electrode connected to a second electrode ofsaid first transistor; a first switching circuit connected between saidfirst word line and said ground voltage for controlling the supply ofthe ground voltage to said first word line; a third transistor having afirst electrode connected to said decoding signal transferring line anda gate electrode for receiving the ground voltage; a fourth transistorhaving a first electrode for receiving said second drive signal, asecond electrode connected to said second word line and a gate electrodeconnected to a second electrode of said third transistor; and a secondswitching circuit for controlling the supply of the ground voltage tosaid second word line in response to the voltage of said decoding signaltransferring line.
 8. A semiconductor memory according to claim 6,further comprising:a second decoding circuit for decoding said addressinformation and for supplying a first drive signal to drive said firstword line via said drive circuit in response to said addressinformation; a third decoding circuit for decoding said addressinformation and supplying a second drive signal to drive said secondword line via said drive circuit in response to said addressinformation; and a buffer circuit connected to a boosted voltage higherthan the power supply voltage and a ground voltage for outputting anoutput signal having said boosted voltage or said ground voltage inresponse to a voltage of said decoding signal transferring line; andwherein said first word line drive circuit transfers said first drivesignal to said first word line in response to the output signal of saidbuffer circuit and transfers the voltage of said first word line to theground voltage when said third decoding circuit supplies said seconddrive signal; and said second drive circuit transfers said second wordline drive signal to said second word line in response to the outputsignal of said buffer circuit and transforms the voltage of said secondword line to the ground voltage when said second decoding circuitsupplies said first drive signal.
 9. A semiconductor memory according toclaim 8, wherein said first word line drive circuit comprisesa firsttransistor of a first conductivity type having a first electrode whichreceives said first drive signal, a second electrode connected to saidfirst word line, and a gate electrode which receives an output of saidbuffer circuit; a second transistor of a second conductivity type havinga first electrode which receives the ground voltage, a second electrodeconnected to said first word line and a gate electrode which receives anoutput of said buffer circuit; and a third transistor of the secondconductivity type connected in parallel with said second transistor andhaving a gate electrode for receiving said second drive signal; andwherein said second drive circuit comprisesa fourth transistor of saidfirst conductivity type having a first electrode which receives saidsecond drive signal, a second electrode connected to said second wordline, and a gate electrode which receives an output of said buffercircuit; a fifth transistor of the second conductivity type having afirst electrode which receives the ground voltage, a second electrodeconnected to said second word line and a gate electrode which receivesan output of said buffer circuit; and a sixth transistor of said secondconductivity type connected in parallel with said fifth transistor andhaving a gate electrode which receives said first drive signal.
 10. Asemiconductor memory for storing data, comprising:a plurality of bitline pairs, each of said bit line pairs transferring data; first,second, third and fourth word lines intersecting at least one of saidbit line pairs; a memory cell array having first and second memory cellgroups, each memory cell group comprising a plurality of memory cellsconnected with said bit line and one of said word lines, each of saidmemory cells being arranged at an intersection of a bit line and a wordline; a first drive circuit for driving said first word line; a seconddrive circuit for driving said second and third word lines; a thirddrive circuit for driving said fourth word line; a first sub decodingcircuit for decoding address information and for outputting a firstdrive signal to drive said first word line via said first drive circuitin response to said address information; a second sub decoding circuitfor decoding said address information and for outputting a second drivesignal to drive said second or third word line via said second drivecircuit in response to said address information; a third sub decodingcircuit for decoding said address information and for outputting a thirddrive signal to drive said fourth word line via said third drive circuitin response to said address information; a decoding signal transferringline for connecting said drive circuits to each other for the activationthereof; a main decoding circuit for decoding said address informationand for activating said decoding signal transferring line; and first andsecond amplification circuits for amplifying voltage differencestransferred from one of said bit line pairs, said first memory cellgroup being arranged between said first and second drive circuits, saidfirst sub decoding circuit beside said first drive circuit, said secondsub decoding circuit beside said second drive circuit, and said firstamplification circuit between said first and second sub decodingcircuits; said second memory cell group being arranged between saidsecond and third drive circuits, said third sub decoding circuit besidesaid third drive circuit, and said second amplification circuit betweensaid second and third sub decoding circuits; and said third drivecircuit being arranged between said main decoding circuit and saidsecond memory cell group.
 11. A semiconductor memory according to claim1 wherein said word line is arranged above said gate electrode, andwherein said first metal layer extends between said word line and thegate electrode.
 12. A semiconductor memory for storing data,comprising:a first wiring layer which includes a pair of bit lines fortransferring data, said first wiring layer extending in a firstdirection; a plurality of word lines formed by a second wiring layerextending in a second direction substantially orthogonal to that of saidpair of bit lines; a control line formed by a third wiring layerextending in the first direction; a decoding signal transferring lineformed by a fourth wiring layer extending in the second direction; amemory cell array comprising a plurality of memory cells, each of saidmemory cells being connected to said pair of bit lines and a word lineat intersections of said pair of bit lines and said word line, eachmemory cell having a transistor; and a gate electrode line extending insaid second direction parallel to and spaced from said word lines, saidgate electrode line being connected to a gate electrode of thetransistor of said memory cell, wherein said gate electrode line isconnected to said word lines at a region other than a region wherein amemory cell is formed by a fifth wiring layer extending in a thirddirection substantially orthogonal to said first and second directions.13. A semiconductor memory according to claim 12, wherein said second,third and fourth wiring layers are made of a metal.